Clock ratio data synchronizers are known and are used to synchronize data moving from one clock frequency domain to another clock frequency domain. For example, clock ratio data synchronizers are known that synchronize data moving from a higher clock frequency domain to a lower clock frequency domain, and vice versa. Currently clock ratio data synchronizers do not provide maximum tolerance between the skews of the clocks of the different clock frequency domains. Maximization of skew tolerance allows for more variation in the clock paths. For example, in cases where both clocks are being generated off-chip, variation between the off-chip clock paths will exist in addition to variation between the on-chip clock paths. As clock frequency increases, the skew tolerance margin (i.e., the maximum allowable difference between the skews) decreases.
With synchronizers used in non-state-of-the-art ICs, the skew tolerance margins are greater because the clocks run at lower frequencies than in state-of-the-art ICs. Consequently, skew tolerance margins were not a big concern. However, with the ever-increasing demand to increase clock frequencies and data rates, current skew tolerance margins are insufficient using previous clock ratio data synchronizers.
Previous synchronizer designs utilize latches. Whatever is on the input of a latch is reflected on the output of the latch when the latch is in the “transparent mode”. In the non-transparent mode of the latch, the output holds whatever value was on the output at the time that the signal that enabled the latch was removed. The transparent nature of the latch can potentially cause problems in the upstream logic in terms of the amount of time that the upstream logic has to make the input to the synchronizer valid. Therefore, it is possible that the upstream logic will not be able to meet setup time requirements. This also causes problems with the downstream logic because the downstream logic in the path of the synchronizer output will not always know when it must be ready to receive data, since the data could change at anytime during the time window over which the latch is transparent. These problems result in the aforementioned clock skew tolerance margin as well as setup time margin problems.
Accordingly, a need exists for a clock ratio data synchronizer that maximizes the skew tolerance margins between the clocks of the different domains, thereby allowing more variation to exist in the clock paths. A need also exists for such a synchronizer that will provide certainty with respect to setup time margins as well as potential increases in setup time margins. There is also a need for such a synchronizer that works well with static timing analyzers, and previous synchronizer designs presented many problems for static timing analysis.